#ifndef __cmpc83xx_h__
#define __cmpc83xx_h__
/**HEADER********************************************************************
* 
* Copyright (c) 2008 Freescale Semiconductor;
* All Rights Reserved
*
* Copyright (c) 2004-2008 Embedded Access Inc.;
* All Rights Reserved
*
* Copyright (c) 1989-2008 ARC International;
* All Rights Reserved
*
*************************************************************************** 
*
* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESSED OR 
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  
* IN NO EVENT SHALL FREESCALE OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 
* THE POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************
*
* $FileName: int_ctrl_mpc83xx.h$
* $Version : 3.8.1.0$
* $Date    : May-12-2011$
*
* Comments:
*
*   This file contains interrupt definitions for the MPC83xx family
*   Verified on MPC8313rdb, MPC8315rdb, MPC8349mITXe and MPC8377rdb
*   Labels denote chip dependencies, but some 8349 labels are simply
*   preserved so we dont have to hunt them down and fix them.
*
*END************************************************************************/

#ifdef __cplusplus
extern "C" {
#endif

/*--------------------------------------------------------------------------*/
/*
**                    CONSTANT DEFINITIONS
*/

/* Interrupt ID numbers */
#define MPC83xx_INT_ID_GTM4         (0x48)
#define MPC83xx_INT_ID_GTM8         (0x49)
#define MPC832x_INT_QE_PORTS        (0x4A)
#define MPC83xx_INT_ID_GPIO         (0x4A)
#define MPC83xx_INT_ID_GPIO2        (0x4B)
#define MPC83xx_INT_ID_DDR          (0x4C)
#define MPC83xx_INT_ID_LBC          (0x4D)
#define MPC83xx_INT_ID_GTM2         (0x4E)
#define MPC83xx_INT_ID_GTM6         (0x4F)
#define MPC83xx_INT_ID_PMC          (0x50)
#define MPC837x_INT_ID_MSIR2        (0x51)
#define MPC837x_INT_ID_MSIR3        (0x52)
#define MPC83xx_INT_ID_TDM_ERR      (0x53)
#define MPC83xx_INT_ID_GTM3         (0x54)
#define MPC83xx_INT_ID_GTM7         (0x55)
#define MPC837x_INT_ID_MSIR4        (0x56)
#define MPC837x_INT_ID_MSIR5        (0x57)
#define MPC837x_INT_ID_MSIR6        (0x58)
#define MPC837x_INT_ID_MSIR7        (0x59)
#define MPC83xx_INT_ID_GTM1         (0x5A)
#define MPC83xx_INT_ID_GTM5         (0x5B)
#define MPC83xx_INT_ID_DMAC_ERR     (0x5E)

/*
** Interrupt Group defintions 
*/

/* Group IDs */
#define MPC83xx_IPIC_INT_GID_SYSA   (0x0)
#define MPC83xx_IPIC_INT_GID_SYSB   (0x1)
#define MPC83xx_IPIC_INT_GID_SYSC   (0x2)
#define MPC83xx_IPIC_INT_GID_SYSD   (0x3)
#define MPC83xx_IPIC_INT_GID_MIXA   (0x10)
#define MPC83xx_IPIC_INT_GID_MIXB   (0x11)

/* Group Type */
#define MPC83xx_IPIC_INT_GTYPE_GROUP  (0)
#define MPC83xx_IPIC_INT_GTYPE_SPREAD (1)


#define MPC83xx_IPIC_RSVD0            (0)
#define MPC83xx_IPIC_RSVD1            (1)
#define MPC83xx_IPIC_RSVD2            (2)
#define MPC83xx_IPIC_RSVD3            (3)
#define MPC83xx_IPIC_RSVD4            (4)
#define MPC83xx_IPIC_RSVD5            (5)
#define MPC83xx_IPIC_RSVD6            (6)
#define MPC83xx_IPIC_RSVD7            (7)

/* System Interrupts Priority Group A */
/* QUICC Engines Only */
#define MPC83xx_IPIC_SYSA_QE_HIGH     (0)
#define MPC83xx_IPIC_SYSA_QE_LOW      (1)

/* eTSEC Engines */
#define MPC83xx_IPIC_SYSA_TSEC1_TX    (0)
#define MPC83xx_IPIC_SYSA_TSEC1_RX    (1)
#define MPC83xx_IPIC_SYSA_TSEC1_ERR   (2)
#define MPC83xx_IPIC_SYSA_TSEC2_TX    (3)
#define MPC83xx_IPIC_SYSA_TSEC2_RX    (4)
#define MPC83xx_IPIC_SYSA_TSEC2_ERR   (5)
#define MPC83xx_IPIC_SYSA_USB_DR      (6)
#define MPC8349_IPIC_SYSA_USB_MPH     (7)   /* mpc834x only */

/* System Interrupts Priority Group B */
/* mpc830x, mpc8315 and mpc837x have Group B */
#define MPC83xx_IPIC_SYSB_TDM_TX      (0)   /* mpc8315 only */
#define MPC83xx_IPIC_SYSB_TDM_RX      (1)   /* mpc8315 only */
#define MPC83xx_IPIC_SYSB_ESDHC       (2)   /* mpc830x and mpc837x only */
#define MPC83xx_IPIC_SYSB_SATA1       (4)   /* mpc8315 and mpc837x only */
#define MPC83xx_IPIC_SYSB_SATA2       (5)
#define MPC837x_IPIC_SYSB_SATA3       (6)   /* mpc837x only */
#define MPC837x_IPIC_SYSB_SATA4       (7)   /* mpc837x only */

/* System Interrupts Priority Group C */
/* mpc830x, mpc8315 and mpc837x have Group C */
#define MPC83xx_IPIC_SYSC_PEX1_CNT    (0)
#define MPC83xx_IPIC_SYSC_PEX2_CNT    (1)   /* No PCI Express2 on mpc8308 */
#define MPC83xx_IPIC_SYSC_DMA1        (2)   /* mpc830x */
#define MPC83xx_IPIC_SYSC_MSIR1       (3)

/* System Interrupts Priority Group D */
#define MPC83xx_IPIC_SYSD_UART1       (0)
#define MPC83xx_IPIC_SYSD_UARTx       (0)
#define MPC83xx_IPIC_SYSD_UART2       (1)
#define MPC83xx_IPIC_SYSD_CAN         (1)
#define MPC83xx_IPIC_SYSD_SEC         (2)
#define MPC83xx_IPIC_SYSD_ETSEC1_1588 (3)   /* not QUICC engines */
#define MPC83xx_IPIC_SYSD_ETSEC2_1588 (4)   /* not QUICC engines */
#define MPC83xx_IPIC_SYSD_I2C1        (5)
#define MPC83xx_IPIC_SYSD_I2C2        (6)   /* not mpc832x */
#define MPC83xx_IPIC_SYSD_SPI         (7)   /* not mpc832x */

/* Mixed Interrupts Priority Group A */
#define MPC83xx_IPIC_MIXA_RTC         (0)
#define MPC83xx_IPIC_MIXA_PIT         (1)
#define MPC83xx_IPIC_MIXA_PCI         (2)   /* not mpc8308 */
#define MPC83xx_IPIC_MIXA_MSIR0       (3)
#define MPC83xx_IPIC_MIXA_IRQ0        (4)
#define MPC83xx_IPIC_MIXA_IRQ1        (5)
#define MPC83xx_IPIC_MIXA_IRQ2        (6)
#define MPC83xx_IPIC_MIXA_IRQ3        (7)

/* 834x is all different */

#define MPC8349_IPIC_MIXA_PCI1        (2)
#define MPC8349_IPIC_MIXA_PCI2        (3)
#define MPC8349_IPIC_MIXA_EXT0        (4)
#define MPC8349_IPIC_MIXA_EXT1        (5)
#define MPC8349_IPIC_MIXA_EXT2        (6)
#define MPC8349_IPIC_MIXA_EXT3        (7)

/* Mixed Interrupts Priority Group B */
#define MPC83xx_IPIC_MIXB_RTC_ALR     (0)
#define MPC83xx_IPIC_MIXB_MU          (1)   /* not on mpc8308 different DMAC */
#define MPC83xx_IPIC_MIXB_SBA         (2)   
#define MPC83xx_IPIC_MIXB_DMA         (3)   /* not on mpc8308 different DMAC */
#define MPC83xx_IPIC_MIXB_IRQ4        (4)   /* no IRQ 4-7 on mpc830x */
#define MPC83xx_IPIC_MIXB_IRQ5        (5)
#define MPC83xx_IPIC_MIXB_IRQ6        (6)
#define MPC83xx_IPIC_MIXB_IRQ7        (7)


/*--------------------------------------------------------------------------*/
/*
**                    DATATYPE DECLARATIONS
*/

typedef struct mpc83xx_int_mask_struct {
   
   uint_32    SIMSR_H; 
   uint_32    SIMSR_L;	
   uint_32    SEMSR;
} MPC83xx_INT_MASK_STRUCT;

typedef struct mpc83xx_int_group_param_struct 
{
	uchar   GID;     /* SYSA/SYSB/SYSC/SYSD/MIXA/MIXB */
	uchar   GTYPE;   /* GROUPED/SPREAD      */ 
	uint_32 PRIO_LIST[8]; /* Relative prioritis in the 
	                         group, 0 - Highest, 7 - Lowest */
} MPC83xx_INT_GROUP_PARAM_STRUCT, _PTR_ MPC83xx_INT_GROUP_PARAM_STRUCT_PTR;

/*-----------------------------------------------------------------------*/
/*
**                    FUNCTION PROTOTYPES AND GLOBAL EXTERNS
*/
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_sysa_param_list;
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_sysb_param_list;
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_sysc_param_list;
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_sysd_param_list;
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_mixa_param_list;
extern MPC83xx_INT_GROUP_PARAM_STRUCT mpc83xx_int_group_mixb_param_list;

extern void _mpc83xx_ipic_init(void);
extern void _mpc83xx_disable_interrupt(uint_32);
extern void _mpc83xx_enable_interrupt(uint_32);
extern void _mpc83xx_external_isr(pointer);
extern void _mpc83xx_ipic_set_group_prios(pointer);

#ifdef __cplusplus
}
#endif

#endif
/* EOF */

